During the 11th meeting of the french speaking workshop on compilation I’ve done a talk (with more question than answers) on « Compilation au vol pour système embarqués contraints » (on the fly compilation for embedded systems)
This meeting was in Aussois, and this year has a focus on security.
The slides used during this presentation
Our work about run-time optimization for Wireless Sensor Network has been presented and published in the 5th International Workshop on Computing and Networking for Internet of Things.
There is news on the DCE 2016 workshop web page. I’ve added the members of the program committee. The deadline for the article submission is : Friday 15 Jan 2016
I was happy to be part of the PhD defense of Safae DAHMANI. Her PhD title is :
During the introduction to the defense
« Modèles et protocoles de cohérence de données, décision et optimisation à la compilation pour des architectures massivement parallèles. »
devant le jury composé de :
- Henri-Pierre Charles Directeur de recherche au CEA Grenoble) / Président
- Raymond Namyst Professeur à l’Université de Bordeaux / Rapporteur
- Gilles Sassatelli Directeur de recherche CNRS, Montpellier / Rapporteur
- Gabriel Antoniu Directeur de recherche à l’INRIA, Rennes /
Safae Dahmani during the defense
- Guy Gogniat Professeur à l’Université de Bretagne Sud /
Directeur de thèse
- Loïc Cudennec
Ingénieur chercheur au CEA Saclay / Encadrant de thèse
The PhD abstract is :
Manycœurs architectures consist of hundreds to thousands of embedded cores, distributed memories and a dedicated network on a single chip. In this context, and because of the scale of the processor, providing a shared memory system has to rely on efficient hardware and software mechanisms and data consistency protocols. Numerous works explored consistency mechanisms designed for highly parallel architectures. They lead to the conclusion that there won’t exist one protocol that fits to all applications and hardware contexts. In order to deal with consistency issues for this kind of architectures, we propose in this work a multi-protocol compilation toolchain, in which shared data of the application can
4 PhD generation together ! Raymond Namyst, Gabriel Antoniu, Loic Cudennec and Safae Dahmani
be managed by different protocols. Protocols are chosen and configured at compile time, following the application behavior and the targeted architecture specifications. The application behavior is characterized with a static analysis process that helps to guide the protocols assignment to each data access. The platform offers a protocol library where each protocol is characterized by one or more parameters. The range of possible values of each parameter depends on some constraints mainly related to the targeted platform. The protocols configuration relies on a genetic-based engine that allows to instantiate each protocol with appropriate parameters values according to multiple performance objectives. In order to evaluate the quality of each proposed solution, we use different evaluation models. We first use a traffic analytical model which gives some NoC communication statistics but no timing information. Therefore, we propose two cycle-based evaluation models that provide more accurate performance metrics while taking into account contention effect due to the consistency protocols communications. We also propose a cooperative cache consistency protocol improving the cache miss rate by sliding data to less stressed neighbors. An extension of this protocol is proposed in order to dynamically define the sliding radius assigned to each data migration. This extension is based on the mass-spring physical model. Experimental validation of different contributions uses the sliding based protocols versus a four-state directory-based protocol.
I’ve done a seminar in the master of the Grenoble Alpes University. during the compilation course done by Jean-Claude Fernandez.
The subject was « Dynamic Compilation Everywhere », computer architecture and dynamic compilation. The course outline was :
- State of the art in
- Computer architecture
- Compilation chains
- Why optimize : Memory herarchy, Out of Order, microcontroller, MPSoC
- Classicals law
- How to profile, mesure performances
Here are the slides of the presentation
I was happy to participate to the committee of the PhD defense of M. Aravind SUKUMARAN RAJAM at the Strasbourg University. The defense was on Thursday Nov 5. 2015. The abstract of his thesis is :
In this thesis, we present our contributions to APOLLO (Automatic speculative POLyhedral Loop Optimizer), which is an automated compiler combining Thread Level Speculation (TLS) and the polyhedral model to optimize codes on the ﬂy. By doing partial instrumentation at runtime, and subjecting it to interpolation, Apollo is able to construct a speculative polyhedral model dynamically. The speculative model is then passed to Pluto -a static polyhedral scheduler-. Apollo then selects one of the statically generated code optimization skeletons and instantiates it. The runtime continuously monitors the code for any dependence violation in a decentralized manner.
Another important contribution of this thesis is our extension of the polyhedral model to codes exhibiting a non linear behavior. Thanks to the dynamic and speculative context oﬀered by Apollo, non-linear behaviors are either modeled using linear regression hyperplanes forming tubes, or using ranges of reached values. Our approach enables the application of polyhedral transformations to non-linear codes thanks to an hybrid centralized-decentralized speculation veriﬁcation system.
The defense committee was composed by :
- M. P. Sadayappan Professor, Ohio State University, USA
- M. Erven ROHOU Directeur de Recherche Inria, Équipe Alf, Rennes, France
- M. Henri Pierre CHARLES Directeur de Recherche informatique au CEA, Grenoble, France
- Philippe CLAUSS Professeur, Université de Strasboug
I’ve done a talk at the conference ACIVS in Catania, Italy. It was during a special session for the COPCAMS european project
This talk was « Binary Code Generation for Multimedia Application on Embedded Platforms »
The abstract was :
<< Multimedia applications such as video compression, image processing, face recognition, run now on embedded platforms. The huge computing power
needed is provided by the evolution of the transistor density and by using specialized accelerators. Theses accelerators are supported by multimedia
Using theses complex instructions can be a nightmare for the engineer
because there is many way to program it, quality of the compiler support
can be random depending on the couple compiler/platform and worse,
performances can be data dependent. Using libraries can be an option if
such library exist and provide enough performances.
In this talk I’ll illustrate the difficulty to generate binary code for this
application domain by practical example of code generation. Then I’ll
show a tool deGoal which is developed in house to resolve these problems. >>
What a wonderfull conference room for a conference on Vision Systems.
I attended to the ESWEEK conference, in Amsterdam, mainly the CASES conference.
I’ve done a talk during the IoT symposium. « Self-optimisation using runtime code generation for Wireless Sensor Networks« , Caroline Quéva, Damien Couroussé and Henri-Pierre Charles.
My slides are now online on the HAL website : https://hal-cea.archives-ouvertes.fr/cea-01240865
Today, compilation day ! October 1, 2015 CEA NanoInnov, Amphitéatre 33, Av. de la Vauve, 91120 Palaiseau. It was announced on the labex persyval web site.
Agenda and CV :
- 10:30-11:30 : Benoit Dupont de Dinechin Séminaire : « Revisiting DSP Acceleration with the Kalray MPPA Manycore Processor »
- 14:00-16:00 : Alexandre Aminot Soutenance de thèse : « Placement de tâches dynamique et flexible sur processeur multi‐coeur asymétrique en fonctionnalités»
- The thesis committee was composed by
- Guy GOGNIAT Professeur Université de Bretagne-Sud – UEB Rapporteur
- Alain PEGATOQUET Maître de conférences Univ. de Nice Sophia Antipolis Rapporteur
- Albert COHEN Directeur de recherche INRIA – ENS Examinateur
- Karine HEYDEMANN Maître de conférences Univ. Pierre et Marie Curie Examinateur
- Vivien QUEMA Professeur Grenoble INP / ENSIMAG Examinateur
- Benoit DUPONT de DINECHIN Directeur de la technologie Kalray Examinateur
- Henri-Pierre CHARLES Directeur Recherche CEA LIST Directeur de thèse
- Yves LHUILLIER Ingénieur Recherche CEA LIST Encadrant de thèse
- Andrea CASTAGNETTI Ingénieur Recherche CEA LIST Encadrant de thèse (invité)
« Compilation day » in Grenoble. A compilation day is a mini workshop which include a talk given by a thesis comittee member followed by the PhD defense.
Agenda and CV
- 10:30-11:30h : Invited talk : Paul Kelly, Imperial College London « Compiler technology for solving PDEs with performance portability«
- 14-16h : PhD defense : Fernando A. Endo « Online auto-tuning for performance and energy through micro-architecture dependent code generation. »
- Fernando thesis dissertation
- Fernando Thesis Slides
- The thesis committee was composed by
- M. Florent de DINECHIN professeur, INSA de Lyon, Rapporteur
- M. Paul KELLY, professeur, Imperial College London, Rapporteur
- M. Frédéric PÉTROT, professeur, Grenoble Institute of Technology, Examinateur
- Mme Karine HEYDEMANN, maître de conférences, Univ. Pierre et Marie Curie, Examinatrice
- M. Henri-Pierre CHARLES, directeur de recherche au CEA, Directeur de thèse
- M. Damien COUROUSSÉ, ingénieur chercheur au CEA, Grenoble, Encadrant de thèse